Clocking architecture for DVFS with low-frequency DLL locking
US10784871B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2019 |
| Grant date | Sep 22, 2020 |
| Priority date | — |
| Expiry date | Jul 31, 2039 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit and corresponding method for dynamic voltage frequency scaling (DVFS) on a chip employ a delay-locked loop (DLL)-based clocking architecture. The circuit comprises a DLL including a fixed delay line path, with a first insertion delay, and variable delay line path, with a second insertion delay, and a clock generator. The clock generator is configured to source a DLL input clock to the fixed and variable delay line paths at a start-up frequency prior to a run-time frequency. The start-up frequency is lower relative to a target frequency for the chip. The run-time frequency is configured based on DVFS, following release of the chip from reset. The chip is configured to be released from reset with the DLL locked at the start-up frequency, enabling the second insertion delay to match the first insertion delay with the DLL locked at the start-up frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.