Thermal infrared sensor array in wafer-level package
US10788370B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2016 |
| Grant date | Sep 29, 2020 |
| Priority date | — |
| Expiry date | Apr 4, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01J2005/123
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A thermal infrared sensor array in a wafer-level package includes at least one infrared-sensitive pixel produced using silicon micro mechanics, comprising a heat-isolating cavity in a silicon substrate surrounded by a silicon edge, and a thin membrane connected to the silicone edge by of thin beams. The cavity extends through the silicon substrate to the membrane, and there are slots between the membrane, the beams and the silicon edge. A plurality of infrared-sensitive individual pixels are arranged in lines or arrays and are designed in a CMOS stack in a dielectric layer, forming the membrane, and are arranged between at least one cover wafer which is designed in the form of a cap and has a cavity and a base wafer. The cover wafer, the silicon substrate and the base wafer are connected to one another in a vacuum-tight manner and enclosing a gas vacuum.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.