Seed operation for memory devices
US10790027B2 · kind B2 · utility
0Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2020 |
| Grant date | Sep 29, 2020 |
| Priority date | — |
| Expiry date | Mar 24, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3427
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a plurality of data lines, a common source, and control logic. The control logic is configured to implement a seed operation by biasing each of the plurality of data lines to a first voltage level with the common source biased to a second voltage level lower than the first voltage level. With each data line biased to the first voltage level, the control logic is configured to float each data line and bias the common source to the first voltage level such that the bias of each data line is boosted above the first voltage level due to capacitive coupling between each data line and the common source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.