3D integrated circuit and methods of forming the same
US10790189B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2018 |
| Grant date | Sep 29, 2020 |
| Priority date | — |
| Expiry date | Nov 13, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01322
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.