Semiconductor package and manufacturing method thereof
US10790210B2 · kind B2 · utility
2Cited by
17References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2018 |
| Grant date | Sep 29, 2020 |
| Priority date | — |
| Expiry date | Oct 25, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package and a manufacturing method are provided. The semiconductor package includes a die, a dummy cube, a stress relaxation layer, an encapsulant and a redistribution structure. The dummy cube is disposed beside the die. The stress relaxation layer covers a top surface of the dummy cube. The encapsulant encapsulates the die and the dummy cube. The redistribution structure is disposed over the encapsulant and is electrically connected to the die. The stress relaxation layer is interposed between the dummy cube and the redistribution structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.