Semiconductor memory device
US10790229B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2018 |
| Grant date | Sep 29, 2020 |
| Priority date | — |
| Expiry date | Aug 29, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/69
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device according to an embodiment includes a substrate; a plate-like first conductivity layer provided above the substrate and extending parallel to a substrate plane to bestride first and second regions; a plate-like second conductivity layer provided above the first conductivity layer to be separated from the first conductivity layer, an end portion of the first conductivity layer has a protruding staircase shape in the first region, the second conductivity layer extending parallel to the first conductivity layer to bestride the first and second regions; a first contact connected to the first conductivity layer at a side surface or a bottom surface of the first conductivity layer and extending from the first conductivity layer toward the substrate, the first contact being connected at a position where the end portion of the first conductivity layer in the first region protrudes, and a diameter size of a portion of the first contact connected at a side surface or a bottom surface of the first conductivity layer having a maximum diameter size; a second contact connected to the second conductivity layer at a side surface or a bottom surface of the second condu…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.