Fan-out semiconductor package
US10790255B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2019 |
| Grant date | Sep 29, 2020 |
| Priority date | — |
| Expiry date | Mar 4, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15156
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fan-out semiconductor package includes a frame comprising a plurality of wiring layers electrically connected to one another, and having a recessed portion having a stopper layer 112aM disposed on a bottom surface of the recessed portion, and a through-hole penetrating through the stopper layer; a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, and disposed in the recessed portion such that the inactive surface opposes the stopper layer; an encapsulant covering at least portions of the frame and the inactive surface of the semiconductor chip, and filling at least a portion of the recessed portion; and an interconnect structure disposed on the frame and the active surface of the semiconductor chip, and comprising a redistribution layer electrically connected to the plurality of wiring layers and the connection pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.