Memory device with a plurality of stacked memory core chips
US10790266B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2019 |
| Grant date | Sep 29, 2020 |
| Priority date | — |
| Expiry date | Mar 11, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminal; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.