Vertical memory device
US10790294B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2017 |
| Grant date | Sep 29, 2020 |
| Priority date | — |
| Expiry date | Sep 16, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
Abstract
A vertical memory device includes a substrate having a cell array region and a connection region positioned on an exterior of the cell array region. Gate electrode layers are stacked on the cell array region and the connection region of the substrate, forming a stepped structure in the connection region. Channel structures are disposed in the cell array region, extending in a direction perpendicular to an upper surface of the substrate, while passing through the gate electrode layers. Dummy channel structures are disposed in the connection region, extending in the same direction as the channel structures, while passing through the gate electrode layers forming the stepped structure. First semiconductor patterns are disposed below the channel structures, and second semiconductor patterns are disposed below the dummy channel structures. The first and second semiconductor patterns include polycrystalline semiconductor materials.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.