Memory cell with top electrode via
US10790439B2 · kind B2 · utility
9Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 20, 2019 |
| Grant date | Sep 29, 2020 |
| Priority date | — |
| Expiry date | May 20, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76811
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a magnetoresistive random access memory (MRAM) device surrounded by a dielectric structure disposed over a substrate. The MRAM device includes a magnetic tunnel junction disposed between a bottom electrode and a top electrode. A bottom electrode via couples the bottom electrode to a lower interconnect wire. A top electrode via couples the top electrode to an upper interconnect wire. A bottom surface of the top electrode via has a first width that is smaller than a second width of a bottom surface of the bottom electrode via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.