Circuit structure to generate back-gate voltage bias for amplifier circuit, and related method
US10790785B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2019 |
| Grant date | Sep 29, 2020 |
| Priority date | — |
| Expiry date | Jan 11, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45731
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure provide a circuit structure. An error amplifier of the structure includes an input terminal coupled to a voltage source, a reference terminal, and an output terminal coupled to a back-gate terminal of a power amplifier. A voltage at the output terminal of the error amplifier indicates a voltage difference between the input terminal and the reference terminal. A logarithmic current source may be coupled to the reference terminal of the error amplifier, the logarithmic current being configured to generate a reference current logarithmically proportionate to a voltage level of the voltage source. A plurality of serially coupled transistor cells, having a shared substrate and coupled between the reference terminal of the error amplifier and ground, each may include a back-gate terminal coupled to the output terminal of the error amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.