Patent · US Active

Method for producing thin MEMS wafers

US10793430B2 · kind B2 · utility

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7Claims
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Key dates

Filing dateSep 14, 2018
Grant dateOct 6, 2020
Priority date
Expiry dateOct 19, 2038

Classification

  • Technology area (CPC B)Performing Operations; Transporting
  • CPC primaryB81C2201/056
  • WIPO fieldMicro-structural and nano-technology
  • WIPO sectorChemistry

Abstract

A method for producing thin MEMS wafers including: (A) providing an SOI wafer having an upper silicon layer, a first SiO2 layer and a lower silicon layer, the first SiO2 layer being situated between the upper silicon layer and the lower silicon layer, (B) producing a second SiO2 layer on the upper silicon layer, (C) producing a MEMS structure on the second SiO2 layer, (D) introducing clearances into the lower silicon layer down to the first SiO2 layer, (E) etching the first SiO2 layer and thus removing the lower silicon layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.