Product performance test binning
US10794952B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2018 |
| Grant date | Oct 6, 2020 |
| Priority date | — |
| Expiry date | Jul 22, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31701
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and associated system. The method includes steps of: (a) a voltage bin is selected from of a set of voltage bins, each voltage bin having a different range of frequencies based on the highest operating frequency and the lowest operating frequency specified for an integrated circuit chip not previously tested; (b) a functional path test is performed on a selected path of a set of testable data paths of the integrated circuit chip not previously tested; (c) if the integrated circuit chip fails the functional path test, then a current supply voltage value is changed to a voltage value associated with a not previously selected voltage bin; (d) a not previously tested path of the set of testable paths is selected. Steps (b), (c) and (d) are repeated until every path of the set of testable paths has been tested.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.