Inventor · Colchester, VT, US

Theodoros E. Anemikos

13Patents

5h-index

18Co-inventors

59Inventor score

Filing activity: Feb 27, 2008 → Jun 13, 2018

Most-cited inventions

Patent	Title	Area	Cited by	Status
US7810054B2	Method of optimizing power usage of an integrated circuit design by tuning selective voltage binning cut point	Physics	10	Active
US8214651B2	Radio frequency identification (RFID) based authentication system and methodology	Electricity	10	Active
US7877714B2	System and method to optimize semiconductor power by integration of physical design timing and product performance measurements	Physics	9	Active
US8421495B1	Speed binning for dynamic and adaptive power control	Electricity	7	Active
US8176323B2	Radio frequency identification (RFID) based authentication methodology using standard and private frequency RFID tags	Electricity	6	Active
US7487487B1	Design structure for monitoring cross chip delay variation on a semiconductor device	Physics	5	Active
US9310426B2	On-going reliability monitoring of integrated circuit chips in the field	Physics	5	Active
US8097474B2	Integrated circuit chip design flow methodology including insertion of on-chip or scribe line wireless process monitoring and feedback circuitry	Emerging Cross-Sectional Technologies	3	Active
US8239811B2	System and method for wireless and dynamic intra-process measurement of integrated circuit parameters	Electricity	2	Active
US7521973B1	Clock-skew tuning apparatus and method	Electricity	2	Active
US10067184B2	Product performance test binning	Physics	2	Active
US9429619B2	Reliability test screen optimization	Emerging Cross-Sectional Technologies	1	Active
US10794952B2	Product performance test binning	Physics	0	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.