Matrix vector multiplier with a vector register file comprising a multi-port memory
US10795678B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2018 |
| Grant date | Oct 6, 2020 |
| Priority date | — |
| Expiry date | Aug 10, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Neural network processors including a vector register file (VRF) having a multi-port memory and related methods are provided. The processor may include tiles to process an N by N matrix of data elements and an N by 1 vector of data elements. The VRF may, in response to a write instruction, store N data elements in a multi-port memory and during each one of out of P clock cycles provide N data elements to each one of P input interface circuits of the multi-port memory comprising an input lane configured to carry L data elements in parallel. During the each one of the P clock cycles the multi-port memory may be configured to receive N data elements via a selected at least one of the P input interface circuits. The VRF may include output interface circuits for providing N data elements in response to a read instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.