Adding delay elements to enable mapping a time division multiplexing circuit on an FPGA of a hardware emulator
US10796048B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2018 |
| Grant date | Oct 6, 2020 |
| Priority date | — |
| Expiry date | Jun 15, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The independent claims of this patent signify a concise description of embodiments. A method of performing hardware emulation of a circuit design is presented. The method includes partitioning a first portion of the circuit design to a first configurable logic chip of a hardware emulator, adding a selection circuit to the circuit design in the first configurable logic chip, and selecting one of a first signal or a second signal during a first clock cycle. The first signal and the second signal are used in the circuit design. The method further includes storing a first value associated with the selected signal during a second clock cycle, and sending the first value to an output pin of the first configurable logic chip during a third clock cycle. This Abstract is not intended to limit the scope of the claims.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.