Memory device and operating method thereof
US10796767B2 · kind B2 · utility
0Cited by
10References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 23, 2018 |
| Grant date | Oct 6, 2020 |
| Priority date | — |
| Expiry date | Nov 23, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a cell array and a page buffer circuit. The cell array includes first and second cell strings respectively connected to first and second bit lines. The page buffer circuit is configured to apply an erase voltage to the first bit line and to allow the second bit line to be in a floating state, when an erase operation is performed on memory cells of the first and second cell strings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.