Etch-stop layer topography for advanced integrated circuit structure fabrication

US10796951B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Andrew W. Yeoh · Portland, US
• Ruth A. Brain · Portland, US
• Michael L. Hattendorf · Beaverton, US
• Christopher P. Auth · Portland, US

Key dates

• Filing date: Dec 30, 2017
• Grant date: Oct 6, 2020
• Expiry date: Dec 30, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0186
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a plurality of conductive interconnect lines in and spaced apart by an inter-layer dielectric (ILD) layer above a substrate. Individual ones of the plurality of conductive interconnect lines have an upper surface below an upper surface of the ILD layer. An etch-stop layer is on and conformal with the ILD layer and the plurality of conductive interconnect lines, the etch-stop layer having a non-planar upper surface with an uppermost portion of the non-planar upper surface over the ILD layer and a lowermost portion of the non-planar upper surface over the plurality of conductive interconnect lines.