Three-dimensional memory device having stressed vertical semiconductor channels and method of making the same

US10797060B2 · kind B2 · utility

Assignee

• Sandisk Technologies, Inc. · US

Inventors

• Rahul Sharangpani · Fremont, US
• Raghuveer S. Makala · Campbell, US
• Adarsh Rajashekhar · Santa Clara, US
• Fei Zhou · Shanghai, CN
• Srikanth Ranganathan · Mountain View, US
• Akio Nishida · Yokkaichi, JP
• Toshihiro Iizuka · Tokyo, JP

Key dates

• Filing date: Dec 17, 2018
• Grant date: Oct 6, 2020
• Expiry date: Dec 17, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B43/40

Abstract

Three-dimensional memory devices include structures that induce a vertical tensile stress in vertical semiconductor channels to enhance charge carrier mobility. Vertical tensile stress may be induced by a laterally compressive stress applied by stressor pillar structure. The stressor pillar structures can include a stressor material such as a dielectric metal oxide material, silicon nitride, thermal silicon oxide or a semiconductor material having a greater lattice constant than that of the channel. Vertical tensile stress may be induced by a compressive stress applied by electrically conductive layers that laterally surround the vertical semiconductor channel, or by a stress memorization technique that captures a compressive stress from sacrificial material layers. Vertical tensile stress can be generated by a source-level pinning layer that prevents vertical expansion of the vertical semiconductor channel. Vertical tensile stress can be induced by using a layer stack including polysilicon and a silicon-germanium alloy for the vertical semiconductor channel.