Semiconductor device
US10797072B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 21, 2019 |
| Grant date | Oct 6, 2020 |
| Priority date | — |
| Expiry date | Feb 21, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/663
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device according to an embodiment includes an N-well region, a first gate electrode, a columnar epitaxial layer, and a first contact. The N-well region includes two P-type impurity diffusion regions. The first gate electrode is provided above the N-well region between the two P-type impurity diffusion regions. The first gate electrode are opposed to the N-well region via a gate insulating film. The columnar epitaxial layer is provided on the P-type impurity diffusion region. The epitaxial layer includes a first semiconductor layer including P-type impurities. The first contact is provided on the first semiconductor layer of the epitaxial layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.