Semiconductor device with fin end spacer dummy gate and method of manufacturing the same
US10797174B2 · kind B2 · utility
1Cited by
12References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2018 |
| Grant date | Oct 6, 2020 |
| Priority date | — |
| Expiry date | Aug 17, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6219
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a plurality of fins on a substrate. A fin liner is formed on an end surface of each of the plurality of fins. An insulating layer is formed on the plurality of fins. A plurality of polycrystalline silicon layers are formed on the insulating layer. A source/drain epitaxial layer is formed in a source/drain space in each of the plurality of fins. One of the polycrystalline silicon layers is formed on a region spaced-apart from the fins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.