Central processing unit with DSP engine and enhanced context switch capabilities
US10802866B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2016 |
| Grant date | Oct 13, 2020 |
| Priority date | — |
| Expiry date | Dec 14, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device has a first central processing unit including a digital signal processing (DSP) engine, and a plurality of contexts, each context having a CPU context with a plurality of registers and a DSP context, wherein the DSP context has control bits and a plurality of DSP registers, wherein after a reset of the integrated circuit device the control bits of all DSP context are linked together such that data written to the control bits of a DSP context is written to respective control bits of all other DSP contexts and only after a context switch to another context and a modification of at least one of the control bits of the another DSP context, the control bits of the another context is severed from the link to form independent control bits of the DSP context.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.