Patent · US Active

Computer processor employing cache memory storing backless cache lines

US10802987B2 · kind B2 · utility

0Cited by

4References

25Claims

0Family size

Assignee

Mill Computing, Inc. · US

Inventors

Roger Rawson Godard · East Palo Alto, US
Arthur David Kahlich · Sunnyvale, US

Key dates

Filing date	Oct 15, 2014
Grant date	Oct 13, 2020
Priority date	—
Expiry date	Feb 16, 2037

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A computer processing system with a hierarchical memory system having at least one cache and physical memory, and a processor having execution logic that generates memory requests that are supplied to the hierarchical memory system. The at least one cache stores a plurality of cache lines including at least one backless cache line.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.