Unified address space for multiple hardware accelerators using dedicated low latency links
US10802995B2 · kind B2 · utility
1Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2018 |
| Grant date | Oct 13, 2020 |
| Priority date | — |
| Expiry date | Nov 27, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/404
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system may include a host processor coupled to a communication bus, a first hardware accelerator communicatively linked to the host processor through the communication bus, and a second hardware accelerator communicatively linked to the host processor through the communication bus. The first hardware accelerator and the second hardware accelerator are directly coupled through an accelerator link independent of the communication bus. The host processor is configured to initiate a data transfer between the first hardware accelerator and the second hardware accelerator directly through the accelerator link.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.