System and method for designing a chip floorplan using machine learning
US10803223B2 · kind B2 · utility
1Cited by
3References
3Claims
0Family size
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Key dates
| Filing date | Nov 2, 2018 |
| Grant date | Oct 13, 2020 |
| Priority date | — |
| Expiry date | Nov 2, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for estimating a floorplan designs based on feedback to machine learning algorithms to accumulate data for improving future floorplan design estimates and reducing design time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.