Memory controller for controlling refresh operation and memory system including the same
US10803919B2 · kind B2 · utility
3Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2018 |
| Grant date | Oct 13, 2020 |
| Priority date | — |
| Expiry date | Dec 27, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4062
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a memory module comprising a plurality of memory devices, and a memory controller suitable for controlling the plurality of memory devices to perform a refresh operation or performing an error correction code (ECC) operation on the plurality of memory devices, according to a refresh operation request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.