Master slave level shift latch for word line decoder memory architecture
US10803949B2 · kind B2 · utility
0Cited by
9References
22Claims
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Key dates
| Filing date | Mar 7, 2019 |
| Grant date | Oct 13, 2020 |
| Priority date | — |
| Expiry date | Mar 7, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clocked driver circuit can include a master-slave level shifter latch and a driver. The master-slave level shifter latch can be configured to receive an input signal upon a first state of a clock signal, latch the input signal upon a second state of the clock signal and generate a level shifted output signal corresponding to the latched input signal. The driver can be configured to receive the level shifted output signal from the master-slave level shifter and drive the output signal on a line. The signal levels of the output signal can be greater than the signal level of the input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.