Microelectronics package with vertically stacked dies

US10804246B2 · kind B2 · utility

Assignee

• Qorvo US, Inc. · US

Inventors

• Julio C. Costa · Oak Ridge, US
• Robert Aigner · Winter Garden, US
• Gernot Fattinger · Sorrento, US
• Dirk Robert Walter Leipold · San Jose, US
• George Maxim · Saratoga, US
• Baker Scott · San Jose, US
• Merrill Albert Hatcher, Jr. · Greensboro, US
• Jon Chadwick · Greensboro, US

Key dates

• Filing date: Jun 11, 2018
• Grant date: Oct 13, 2020
• Expiry date: Jun 11, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/15313
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The present disclosure relates to a microelectronics package with vertically stacked flip-chip dies, and a process for making the same. The disclosed microelectronics package includes a module board, a first thinned flip-chip die with a through-die via, a second flip-chip die with a package contact at the bottom, and a mold compound. Herein, a top portion of the through-die via is exposed at top of the first thinned flip-chip die. The first thinned flip-chip die and the mold compound reside over the module substrate. The mold compound surrounds the first thinned flip-chip die and extends above the first thinned flip-chip die to define an opening. The second flip-chip die, which has a smaller plane size than the first thinned flip-chip die, resides within the opening and is stacked with the first thinned flip-chip die by coupling the package contact to the exposed top portion of the through-die via.