Three dimensional integrated circuit
US10804252B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2020 |
| Grant date | Oct 13, 2020 |
| Priority date | — |
| Expiry date | Feb 14, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a device includes providing a first substrate having a first area and a second area, forming a range compensating material over the first substrate so that the first material is disposed over the first area and not disposed over the second area, implanting ions into the first area and the second area to form first and second cleave planes at first and second depths, respectively, each of the first and second cleave planes being defined by a concentration of the implanted ions, removing the range compensating material, and cleaving the first substrate along a cleave profile including the first and second cleave planes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.