Memory array comprising memory cells of Z2-FET type
US10804275B2 · kind B2 · utility
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23Claims
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Key dates
| Filing date | Nov 26, 2018 |
| Grant date | Oct 13, 2020 |
| Priority date | — |
| Expiry date | Apr 26, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D18/655
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array includes memory cells of Z2-FET type arranged in rows and columns, wherein each memory cell includes a MOS-type selection transistor and a first region of a first conductivity type that is shared in common with a drain region of the first conductivity type of the selection transistors. The selection transistors of a same column of the memory array have a common drain region, a common source region, and a common channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.