Configurable security memory region
US10809925B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2019 |
| Grant date | Oct 20, 2020 |
| Priority date | — |
| Expiry date | Jan 28, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1458
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device comprises a memory array with I/O path and security circuitry coupled to the I/O path of the memory array. The memory device comprises control circuitry, responsive to configuration data, to invoke the security circuitry. The memory device comprises a configuration store, storing the configuration data accessible by the control circuitry to specify location and size of a security memory region in the memory array. Responsive to an external command and the configuration data, the control circuitry can be configured to invoke the security circuitry on an operation specified in the external command in response to accesses into the security memory region, or to not invoke the security circuitry in response to accesses to outside the security memory region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.