System and method for operating a DRR-compatible asynchronous memory module
US10810144B2 · kind B2 · utility
1Cited by
9References
20Claims
0Family size
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Key dates
| Filing date | Oct 4, 2016 |
| Grant date | Oct 20, 2020 |
| Priority date | — |
| Expiry date | Aug 8, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2245
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes: providing a DDR interface between a host memory controller and a memory module; and providing a message interface between the host memory controller and the memory module. The memory module includes a non-volatile memory and a DRAM configured as a DRAM cache of the non-volatile memory. Data stored in the non-volatile memory of the memory module is asynchronously accessible by a non-volatile memory controller of the memory module, and data stored in the DRAM cache is directly and synchronously accessible by the host memory controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.