Non-volatile memory with fast data cache transfer scheme
US10811082B1 · kind B1 · utility
5Cited by
13References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2019 |
| Grant date | Oct 20, 2020 |
| Priority date | — |
| Expiry date | Jun 24, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a non-volatile memory circuit, read and write performance is improved by increasing the transfer rate of data through the cache buffer during read and write operations. In an array structure where memory cells are connected along bit lines, and the bit lines organized into columns, pairs of data words are stored interleaved on the bit lines of a pair of columns. Data is transferred in and out of the read and write circuit on an internal bus structure, where part of the transfer of one word stored on a pair of columns can overlap with part of the transfer of another word, accelerating transfer times for both read and write.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.