Semiconductor device having buried gate structure and method for fabricating the same
US10811260B2 · kind B2 · utility
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12Claims
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Key dates
| Filing date | Apr 12, 2019 |
| Grant date | Oct 20, 2020 |
| Priority date | — |
| Expiry date | Apr 12, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor device includes: forming a gate trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the gate trench; forming a first work function layer over the gate dielectric layer; doping a work function adjustment element to form a second work function layer which overlaps with the sidewalls of the gate trench; forming a gate conductive layer that partially fills the gate trench; and forming doped regions inside the semiconductor substrate on both sides of the gate trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.