Footing removal in cut-metal process
US10811320B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2018 |
| Grant date | Oct 20, 2020 |
| Priority date | — |
| Expiry date | Jul 28, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes forming a gate stack, which includes a first portion over a portion of a first semiconductor fin, a second portion over a portion of a second semiconductor fin, and a third portion connecting the first portion to the second portion. An anisotropic etching is performed on the third portion of the gate stack to form an opening between the first portion and the second portion. A footing portion of the third portion remains after the anisotropic etching. The method further includes performing an isotropic etching to remove a metal gate portion of the footing portion, and filling the opening with a dielectric material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.