Method and assembly for mitigating short channel effects in silicon carbide MOSFET devices
US10811494B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2018 |
| Grant date | Oct 20, 2020 |
| Priority date | — |
| Expiry date | Nov 5, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8325
Abstract
A power transistor assembly and method of mitigating short channel effects in a power transistor assembly are provided. The power transistor assembly includes a first layer of semiconductor material formed of a first conductivity type material and a hard mask layer covering at least a portion of the first layer and having a window therethrough exposing a surface of the first layer. The power transistor assembly also includes a first region formed in the first layer of semiconductor material of a second conductivity type material and aligned with the window, one or more source regions formed of first conductivity type material within the first region and separated by a portion of the first region, and an extension of the first region extending laterally through the surface of the first layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.