Resistive random access memory
US10811603B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2019 |
| Grant date | Oct 20, 2020 |
| Priority date | — |
| Expiry date | Feb 19, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8836
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A resistive random access memory (RRAM) is provided. The RRAM includes a lower electrode, an upper electrode, a first variable resistance layer and a second variable resistance layer. The lower electrode is disposed on a substrate, and is a single electrode or a pair of electrodes electrically connected to each other. The upper electrode is disposed on the lower electrode, and overlaps the lower electrode. The first variable resistance layer and the second variable resistance layer are disposed on the substrate. At least a portion of the first variable resistance layer is disposed between the lower electrode and the upper electrode, and at least a portion of the second variable resistance layer is disposed between the lower electrode and the upper electrode and connected to the first variable resistance layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.