Voltage multiplier circuit with a common bulk and configured for positive and negative voltage generation
US10811960B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 6, 2019 |
| Grant date | Oct 20, 2020 |
| Priority date | — |
| Expiry date | Sep 6, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M3/078
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A voltage doubler circuit supports operation in both a positive voltage boosting mode to positively boost voltage from a first node to a second node and a negative voltage boosting mode to negatively boost voltage from the second node to the first node. The voltage doubler circuit is formed by transistors of a same conductivity type that share a common bulk that is not tied to a source of any of the voltage doubler circuit transistors. A bias generator circuit is coupled to receive a first voltage from the first node and second voltage from the second node. The bias generator circuit operates to apply a lower one of the first and second voltages to the common bulk.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.