Output signal control during retention mode operation
US10812081B1 · kind B1 · utility
0Cited by
13References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2019 |
| Grant date | Oct 20, 2020 |
| Priority date | — |
| Expiry date | Sep 27, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018507
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A computer system may include circuit blocks that may operate in different operating modes. When operating in a retention mode, a voltage level of a local power supply node for a particular circuit block may be less than a voltage level of the local power supply node when the particular circuit block is operating in an active mode. An output buffer circuit may be configured to generate, when the particular circuit block is operating in retention mode, an output signal using a circuit signal generated by the particular circuit block, and a voltage level corresponding to the active mode of operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.