Apparatus and method to reduce lock time via frequency band calibration
US10812089B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2019 |
| Grant date | Oct 20, 2020 |
| Priority date | — |
| Expiry date | Mar 18, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/24
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Apparatus and associated methods relating to reducing lock time include pre-calibrating and storing phase-locked loop (PLL) and/or injection-locked oscillator (ILO) adaptation values during startup and loading the pre-calibrated values during rate change. In an illustrative example, an integrated circuit may include a controllable frequency circuit operable at frequencies within each of a plurality of frequency bands. A data store may store operational settings associated with each frequency of the plurality of frequency bands. A state machine may be coupled to the controllable frequency circuit and the data store configured to select a predetermined frequency band in response to a command signal, retrieve, from the data store, operational settings associated with the predetermined frequency band, and, apply the retrieved operational settings to the controllable frequency circuit. With the pre-calibration, PLL and/or ILO lock times during rate change in a multi-rate serializer/deserializer (SERDES) link may be advantageously reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.