Self-test apparatuses having distributed self-test controller circuits and controller circuitry to control self-test execution based on self-test properties and method thereof
US10816595B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 2018 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | Feb 14, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3187
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A self-test apparatus for use in an electronic system includes an inter-chip communication bus, a plurality of circuit devices, circuitry including memory, and test controller circuitry. The plurality of circuit devices each has a distributed self-test controller circuit and analog, mixed signal or digital circuit elements. The distributed self-test controller circuits are integrated communicatively via the inter-chip communication bus and negotiate a self-test protocol with each other. The circuitry including memory stores self-test properties of the circuit elements, the self-test properties corresponding to an identifier of each of the circuit elements and a manner or protocol in which the circuit elements are tested. The test controller circuitry collects the self-test properties of the circuit elements and controls execution of the self-test according to the negotiated self-test protocol and the self-test properties.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.