Patent · US Active

Power savings for neural network architecture with zero activations during inference

US10817042B2 · kind B2 · utility

29Cited by

1References

22Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Kinchit Desai · Folsom, US
Sanjeev Jahagirdar · Folsom, US
Prasoonkumar Surti · Folsom, US
Joydeep Ray · Folsom, US

Key dates

Filing date	Sep 27, 2018
Grant date	Oct 27, 2020
Priority date	—
Expiry date	Dec 14, 2038

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Embodiments are generally directed to providing power savings for a neural network architecture with zero activations during inference. An embodiment of an apparatus includes one or more processors including one or more processor cores; and a memory to store data for processing including neural network processing, wherein the apparatus to perform a fast clear operation to initialize activation buffers for a neural network by updating metadata to indicate zero values, the neural network including a plurality of layers, wherein the apparatus is to compare outputs for the neural network to the metadata values and to write an output to memory only if the output is non-zero.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.