Managing commit order for an external instruction relative to two unissued queued instructions
US10817300B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2018 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | Jan 18, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/683
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a pipeline configured for out-of-order issuing, handling translation of virtual addresses to physical addresses includes: storing translations in a translation lookaside buffer (TLB), and updating at least one entry in the TLB based at least in part on an external instruction received from outside a first processor core. Managing external instructions includes: updating issue status information for each of multiple instructions stored in an instruction queue, processing the issue status information in response to receiving a first external instruction to identify at least two instructions in the instruction queue, including a first queued instruction and a second queued instruction. An instruction for performing an operation associated with the first external instruction is inserted into a stage of the pipeline so that the operation associated with the first external instruction is committed before the first queued instruction is committed and after the second queued instruction is committed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.