Interruptible translation entry invalidation in a multithreaded data processing system
US10817434B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2018 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | Apr 24, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/683
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor core among the plurality of processor cores initiates invalidation of translation entries buffered in the plurality of processor cores by executing a translation invalidation instruction in an initiating hardware thread. The processor core also executes, in the initiating hardware thread, a synchronization instruction following the translation invalidation instruction in program order that determines completion of invalidation, at all of the plurality of processor cores, of the translation entries specified by the translation invalidation instruction and draining of any memory referent instructions whose target addresses have been translated by reference to the translation entries. A register is updated to a state based on a result of the determination. The processor core branches execution to re-execute the synchronization instruction based on the state of the register indicating that the translation entries are not invalidated at all of the plurality of processor cores.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.