Inventor · Ossining, NY, US

Cathy May

38Patents
12h-index
56Co-inventors
84Inventor score

Filing activity: Apr 17, 1998 → Sep 30, 2019

Most-cited inventions

PatentTitleAreaCited byStatus
US6202130A Data processing system for processing vector data and method therefor Physics 111 Expired
US8010763B2 Hypervisor-enforced isolation of entities within a single logical partition's virtual address space Physics 51 Active
US7904661B2 Data stream prefetching in a microprocessor Physics 26 Active
US7389400B2 Apparatus and method for selectively invalidating entries in an address translation cache Physics 21 Active
US8615644B2 Processor with hardware thread control logic indicating disable status when instructions accessing shared resources are completed for safe shared resource condition Physics 19 Active
US8544022B2 Transactional memory preemption mechanism Physics 17 Active
US7350029B2 Data stream prefetching in a microprocessor Physics 17 Expired
US9785557B1 Translation entry invalidation in a multithreaded data processing system Physics 16 Active
US10067713B2 Efficient enforcement of barriers with respect to memory move sequences Physics 16 Active
US7949859B2 Mechanism for avoiding check stops in speculative accesses while operating in real mode Physics 14 Active
US7370177B2 Mechanism for avoiding check stops in speculative accesses while operating in real mode Physics 13 Expired
US8140759B2 Specifying an access hint for prefetching partial cache block data in a cache hierarchy Physics 12 Active
US10387686B2 Hardware based isolation for secure execution of virtual machines Physics 11 Active
US9047079B2 Indicating disabled thread to other threads when contending instructions complete execution to ensure safe shared resource condition Physics 10 Active
US7143267B2 Partitioning prefetch registers to prevent at least in part inconsistent prefetch information from being stored in a prefetch register of a multithreading processor Physics 9 Expired
US7802252B2 Method and apparatus for selecting the architecture level to which a processor appears to conform Physics 9 Active
US9772945B1 Translation entry invalidation in a multithreaded data processing system Physics 7 Active
US9430166B2 Interaction of transactional storage accesses with other atomic semantics Physics 6 Active
US7822942B2 Selectively invalidating entries in an address translation cache Physics 6 Active
US6823445B2 Limiting concurrent modification and execution of instructions to a particular type to avoid unexpected results Physics 4 Expired
US10817434B2 Interruptible translation entry invalidation in a multithreaded data processing system Physics 3 Active
US8424015B2 Transactional memory preemption mechanism Physics 3 Active
US9367264B2 Transaction check instruction for memory transactions Physics 1 Active
US9244846B2 Ensuring causality of transactional storage accesses interacting with non-transactional storage accesses Physics 1 Active
US9626187B2 Transactional memory system supporting unbroken suspended execution Physics 1 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.