Queue-based wear leveling of memory components
US10817435B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2019 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | Jun 10, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for wear leveling memory elements in a memory component of a memory subsystem is described. The method includes a memory subsystem receiving a write request that includes user data and a logical address, removing a next physical address from a next address queue, which stores physical addresses that are designated to be used for fulfilling write requests, and writing the user data to the next physical address in the memory component. Further, the memory subsystem locates, in a logical-to-physical table, an entry associated with the logical address of the write request and includes an old physical address that is mapped to the logical address of the write request. The memory subsystem adds the old physical address to a disposal address queue, wherein the disposal address queue stores physical addresses that are not designated to be used for fulfilling write requests.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.