Method and apparatus for camouflaging an integrated circuit using virtual camouflage cells
US10817638B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2019 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | Mar 25, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and an apparatus for camouflaging an application specific integrated circuit are disclosed. The ASIC comprises a circuit comprising a plurality of interconnected functional logic cells performing a logical function. In one embodiment, the method comprises accepting a coded description of the circuit, wherein the coded description describes the circuit in terms of components comprising a sequential logic component and a virtual camouflage component, generating a logical description of the circuit, the logical description of the circuit comprising a logical description of the virtual camouflage component, and replacing, in the logical description of the circuit, the logical description of the virtual camouflage component with a logical description of a functionally equivalent technology-dependent camouflaged component.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.