Plane polishing method of silicon wafer and processing method of silicon wafer
US10818511B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2019 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | Sep 6, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/463
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The disclosure provides a plane polishing method and a processing method of the silicon wafer. The plane polishing method includes steps of: depositing a hard mask on a silicon substrate to form a silicon wafer base material; forming an opening on the hard mask by photolithography or etching; carrying out an oxidation reaction on a portion of the silicon substrate exposed by the opening, forming an oxide layer having a bottom embedded in the silicon substrate and a top protruding and exposed outside the hard mask by oxidizing the silicon substrate; and polishing the oxide layer by chemical mechanical planarization. In the present disclosure, the surface formed by the oxide layer and the hard mask flat is flat, without a recess even in the case of large structures, thereby precisely controlling a shape and a depth of the cavity in accordance with an oxidation rate on a silicon substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.