Semiconductor structure and testing method thereof
US10818562B2 · kind B2 · utility
4Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2018 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | Nov 12, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/34
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for testing a semiconductor structure includes forming a dielectric layer over a test region of a substrate. A cap layer is formed over the dielectric layer. The dielectric layer and the cap layer are annealed. The annealed cap layer is removed. A ferroelectricity of the annealed dielectric layer is in-line tested.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.