Semiconductor device and method for controlling gate profile using thin film stress in gate last process
US10818657B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2016 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | Sep 25, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
Abstract
There is provided a semiconductor device capable of adjusting profiles of a gate electrode and a gate spacer using a hybrid interlayer insulating film. The semiconductor device includes a gate electrode on a substrate, a gate spacer being on a sidewall of the gate electrode and including an upper portion and a lower portion, a lower interlayer insulating film being on the substrate and overlapping with the lower portion of the gate spacer, and an upper interlayer insulating film being on the lower interlayer insulating film and overlapping with the upper portion of the gate spacer, wherein the lower interlayer insulating film is not interposed between the upper interlayer insulating film and the upper portion of the gate spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.